`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 24.08.2023 20:22:01
// Design Name: 
// Module Name: sim_id
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////
`timescale 1ns/1ps

module sim_id();
    reg rst;
    reg[31:0] inst_i;
    reg[31:0] reg1_data_i;
    reg[31:0] reg2_data_i;
    wire reg1_read_o;
    wire reg2_read_o;
    wire[4:0] reg1_addr_o;
    wire[4:0] reg2_addr_o;
    wire[7:0] aluop_o;
    wire[2:0] alusel_o;
    wire[31:0] reg1_o;
    wire[31:0] reg2_o;
    wire[4:0] wd_o;
    wire wreg_o;

    parameter period = 100;
    
    cpu_id cpu_id_0(
        .rst(rst),
        .inst_i(inst_i),
        .reg1_data_i(reg1_data_i),
        .reg2_data_i(reg2_data_i),
        .reg1_read_o(reg1_read_o),
        .reg2_read_o(reg2_read_o),
        .reg1_addr_o(reg1_addr_o),
        .reg2_addr_o(reg2_addr_o),
        .aluop_o(aluop_o),
        .alusel_o(alusel_o),
        .reg1_o(reg1_o),
        .reg2_o(reg2_o),
        .wd_o(wd_o),
        .wreg_o(wreg_o)
    );

    always begin
        rst = 1'b1;
        inst_i = 32'b00110110001100010101010101010101;
        reg1_data_i = 32'h01010101;
        reg2_data_i = 32'h10101010;
        #(period/2);
        rst = 1'b0;
        #(period);
        inst_i = 32'b00110100001100011111000011110000;
        reg1_data_i = 32'h00001111;
        reg2_data_i = 32'h00000000;
        #(period);
    end

endmodule
